Constant Current Limiting Charger Circuit

This circuit usesLM723Cregulator piece made of a constant current limiting charger. For charging a 12V sealed lead-acid batteries.
LM723C products of National Semiconductor Corporation in the United States, its stable output voltage of 12V DC, maximum output current is 420mA.

Simulated Inductor Circuit

In the constant current excitation, the voltage drop that flows through the  inductor , the voltage as the frequency increases. An active device can be used as an inductor, and its output as the frequency increases. This circuit and the effective inductance (L = R1R2C) to produce a feedback. The Q of the inductor depends on the R1 equal to R2,. At the same time, the forward and reverse feedback path of the amplifier are the same.

Comes from http://www.hqew.net/circuit-diagram/Simulated-Inductor-Circuit_2255.html

AD9279 - Octal LNA/VGA/AAF/ADC and CW I/Q Demodulator

The  AD9279 is designed for low cost, low power, small size, and ease of use for medical ultrasound and automotive radar. It contains eight channels of a variable gain amplifier (VGA) with a low noise preamplifier (LNA), an antialiasing filter (AAF), an analog-to-digital converter (ADC), and an I/Q demodulator with programmable phase rotation.

Each channel features a variable gain range of 45 dB, a fully differential signal path, an active input preamplifier termination, and a maximum gain of up to 52 dB. The channel is optimized for high dynamic performance and low power in applications where a small package size is critical.

The LNA has a single-ended-to-differential gain that is selectable through the SPI. Assuming a 15 MHz noise bandwidth (NBW) and a 21.3 dB LNA gain, the LNA input SNR is roughly 94 dB. In CW Doppler mode, each LNA output drives an I/Q demod-ulator that has independently programmable phase rotation with 16 phase settings.

Power-down of individual channels is supported to increase battery life for portable applications. Standby mode allows quick power-up for power cycling. In CW Doppler operation, the VGA, AAF, and ADC are powered down. The ADC contains several features designed to maximize flexibility and minimize system cost, such as a programmable clock, data alignment, and programmable digital test pattern generation. The digital test patterns include built-in fixed patterns, built-in pseudo random patterns, and custom user-defined test patterns entered via the serial port interface.

AD9279 Main Features:
1. 8 channels of LNA, VGA, AAF, ADC, and I/Q demodulator
2. Low power: 141 mW per channel, TGC mode, 40 MSPS;
3. 60 mW per channel, CW mode
4. 10 mm × 10 mm, 144-ball CSP-BGA
5. TGC channel input-referred noise: 0.8 nV/√Hz, max gain
6. Flexible power-down modes
7. Fast recovery from low power standby mode: <2 μs
8. Overload recovery: <10 ns
9. Low noise preamplifier (LNA)
10. Input-referred noise: 0.75 nV/√Hz, gain = 21.3 dB
11. Programmable gain: 15.6 dB/17.9 dB/21.3 dB
12. 0.1 dB compression: 1000 mV p-p/ 750 mV p-p/450 mV p-p
13. Dual-mode active input impedance matching
14. Bandwidth (BW): >100 MHz
15. Variable gain amplifier (VGA)
16. Attenuator range: 45 dB to 0 dB
17. Postamp gain (PGA): 21 dB/24 dB/27 dB/30 dB
18. Linear-in-dB gain control
19. Antialiasing filter (AAF)
20. Programmable second-order LPF from 8 MHz to 18 MHz
21. Programmable HPF
22. Analog-to-digital converter (ADC)
23. SNR: 70 dB, 12 bits up to 80 MSPS
24. Serial LVDS (ANSI-644, low power/reduced signal)
25. CW mode I/Q demodulator
26. Individual programmable phase rotation
27. Output dynamic range per channel: >160 dBc/√Hz
28. Output-referred SNR: 155 dBc/√Hz,1 kHz offset,3 dBFS

Figure 1: AD9279 Functional Block Diagram



Figure 2: AD9279 Single Simplified Block Diagram


Figure 3: AD9279 Simplifies Block Diagram of the Ultrasound System


Figure 4: AD9279 Transformer-coupled Differential Clock Circuit


Figure 5: AD9279 Differential PECL Sampling Clock Circuit


Figure 6: AD9279 Differential LVDS Sampling Clock Circuit


Figure 7: AD9279 Single-ended 1.8V CMOS Sampling Clock Circuit


Figure 8: AD9279 Single-ended 3.3V CMOS Sampling Clock Circuit


Figure 9: AD9279 CW Mode I / O Output Interface to Connect a Typical Circuit

How to DIY a Miniature Earphone

f you are interested in DIY electronic products, you can't miss reading this article because it is to show you how a miniature earphone is made. Now, let's begin!

Below is the circuit diagram of the miniature receptor.

     

The mini receptor that is the miniature earphone is only a quarter of a coin. Most of the materials on surface are 0402 resistor and  capacitor. Therefore, the welding requirements are high.

On the left is a  connector  of a charger and it is used for micro lithium battery charging. On the right is an inductance made by oneself. The middle is chip TDA7021.

Below is an earphone mic. Take it apart and put a board and battery into it.

 

The lithium battery (3V) and outer skin of the earphone are as below picture shows.

 Please see the below chart. How small the earphone is!

Put the receptor circuit board into the outer skin of the earphone. The underneath is the earphone speaker, middle is battery and the up is receptor. (As below)

Below is the diagram for PCB's top layer of the miniature receptor.

Below is the diagram for bottom layer of the miniature receptor.

This miniature receptor consists of double layer PCB. Drill a hole as slim as your hair in the PCB. You need to grind the 0.5mm swivel to 0.22mm. Be careful for it is so easy to broken.

Finally, the miniature earphone is completed.